A static random access memory (SRAM) device is formed with memory cells which typically uses six MOSFETs to store each memory bit. A memory cell includes a wordline that controls two access transistors and two bitlines. The access transistors control access to a storage cell during read and write operations. More specifically, the access transistors control whether a storage cell should be exposed to the bitlines which are used to transfer data during read and write operations.
In each memory cell, the data is stored on four transistors that form two cross-coupled inverters that each have a pull-up PFET transistor and a pull-down NFET transistor. The interconnection node for the two transistors of each inverter is connected to the gate terminals of the two transistors of the other inverter. More specifically, the gate terminals of the transistors of the first inverter are connected to a first node, which is the series connection point of the drain terminals of the second inverter. Similarly, the gate terminals of the transistors of the second inverter are connected to a second node, which is the series connection point of the drain terminals of the first inverter. Additionally, each inverter is coupled to a bitline via an access transistor.
An SRAM memory cell has three operating states: standby, read, and write. During the standby state, the wordline is not asserted (i.e., the voltage remains in its default state) and the access transistors disconnect the cross-coupled inverters from the bitlines. However, the cross-coupled inverters will continue to retain the stored data so long as they remain connected to a power supply. As such, the data will be lost if the power supply is disconnected.
During a read operation, both the bitlines are precharged and the wordline is asserted, thereby activating the access transistors. The values stored in the nodes of the inverters are transferred to the bitlines by leaving one bitline at its precharged value and discharging the second bitline through the access transistor and pull-down transistor. Consequently, the precharged bitline will be drawn to the value stored in the memory cell.
During a write operation, the value to be written to the memory cell is applied to the bitlines. The wordline is then asserted (i.e., the voltage swings from its default state to a predetermined voltage) thereby activating the access transistors and exposing the memory cell to the bitlines. As such, the value of the bitlines is then written into the memory cell. However, the voltage of the bitlines must be sufficiently high enough to override the previous state of the cross-coupled inverters. More specifically, the bitlines voltage swing must be sufficiently large enough to write into the memory cell, thereby increasing power consumption.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.